1. Field of the Invention
The invention relates to the field of MOS storage devices, particularly those employing floating gates.
2. Prior Art
Metal-oxide-semiconductor (MOS) storage devices which employ floating gates are known in the art. Some of these devices use tunneling to transfer charge from the substrate to the floating gate. (See U.S. Pat. No. 3,500,142) These devices require a relatively thin oxide between the floating gate and the substrate (e.g. 50A). This thin oxide is not only difficult to fabricate, but also prevents long term storage. Other floating gate storage devices employ avalanche injection to transport charge from the substrate to the floating gate. One such device is disclosed in U.S. Pat. No. 3,660,819. For this device a relatively thick oxide is employed to separate the floating gate from the substrate (e.g. 1,000A), making this device practical to fabricate and capable of providing long term storage. This latter device is commercially employed in electrically programmable read-only memories. Charge is removed from these devices by subjecting them to ultraviolet radiation.
Numerous devices have been proposed which permit electrical removal of charge from a floating gate by avalanche injection and other phenomena. This removal permits the storage device to be both electrically programmed and erased. Such floating gate devices including devices which employ two other gates are disclosed in U.S. Pat. No. 3,825,946. In copending application Ser. No. 613,130, filed Sept. 15, 1975, now abandoned, entitled "Electrically Programmable and Erasable MOS Device" and assigned to the assignee of this application, a device is described which is electrically erased by avalanche injection. This MOS device includes n-type source and drain regions disposed in a p-type substrate, and a p-type polycrystalline silicon floating gate. A control gate is also employed for charging and discharging the floating gate.
Tunneling has not been employed in the prior art in practical storage devices for removing charge from a floating gate. Tunneling either required too thin an oxide, or too high a potential. The present invention employs tunneling for discharging a floating gate through a relatively thick oxide, without a high potential.
In U.S. Pat. No. 3,996,657, a double self-aligned method is described for forming the source and drain regions of a floating gate device while doping the gates. Through a predeposition step a lightly doped secondary source and drain region are formed in alignment with the floating gate prior to the formation of the primary source and drain region in alignment with the second gate. The process described in this patent is employed for fabricating the device of the present invention with one significant variation as will be described.